preliminary datasheet LP6205S LP6205SC00 ver. 1.0 datasheet jul.-2013 www.lowpowersemi.com page 1 of 5 high efficiency boost dc/dc regulator general description the lp6205 is a current mode boost dc-dc converter. its pwm circuitry with built-in 0.3 ? ,24v,1.5a current power mosfet makes this converter highly power efficiently. selectable high switching frequency allows faster loop response and easy filtering with a low noise output. the non-inverting input its error amplifier is connected to an internal 1.25v precision reference voltage. soft-start time can be programmed with an external capacitor, which sets the input current ramp rate. current mode control and external compensation network make it easy and flexible to stabilize the system. ordering information LP6205S - f: pb-free package type b6: sot23-6 applications ? alk. battery products ? li-ion battery products ? host/otg 5v output ? hdmi power supply marking information please see website:www.lowpowersemi.com. features ? 1.3v start-up input voltage ? output up to 1.5a ? zero shutdown mode supply current ? 94% efficiency ? up to 1.2mhz switching frequency ? using internal power switches ? small sot23-6 package typical application circuit pin configurations LP6205Sb6f 5 3 2 4 1 6 vdd pgnd sw fb gnd en 10uh r1 100k r1 1m 1uf vout_5 v r2 33 k 1uf 22pf r1 110 k + cout 22uf*3 22pf + 22uf ss24 vin(3.6-5v) o n/off sot23-6 top view
preliminary datasheet LP6205S LP6205SC00 ver. 1.0 datasheet jul.-2013 www.lowpowersemi.com page 2 of 5 functional pin description pin number pin name function sot23-6 1 gnd ground. 2 sw switch pin. 3 gnd ground. 4 fb feedback 5 vdd power pin. 6 en enable pin function block diagram
preliminary datasheet LP6205S LP6205SC00 ver. 1.0 datasheet jul.-2013 www.lowpowersemi.com page 3 of 5 absolute maximum ratings supply input voltage------------------------------------------------------------------------------------------------------- 6v sw pin switch voltage--------------------------------------------------------------------------------- ? 0.3v to (vout + 0.8v) other i/o pin voltages---------------------------------------------------------------------------------- ? 0.3v to (vout + 0.3v) sw pin switch current ------------------------------------------------------------------------------------------------------ 1.5a sw pin voltage(max) ------------------------------------------------------------------------------------------------------ 3 0v lead temperature (soldering, 10 sec.) ------------------------- ---------------------------------------------------------260c storage temperature range ------------------------------------- -------------------------------------------- ?65c to 150c esd susceptibility hbm (human body mode) ----------------------------------------- -----------------------------------------------------------2kv mm(machine-mode)----------------------------------------------- ------------------------------------------------------------200 v recommended operating conditions operation ambient temperature range---------------------------- -------------------------------------- ?40c to 85c electrical characteristics (v in = 1.5v, vdd set to 3.3v, load current = 0, ta = 25c, unless otherwise specified) parameter test conditions min typ max units start-up voltage il = 1ma 2.5 v operating vdd range vdd pin voltage 2.5 6.5 v no load current i (v in ) v in = 2v, v out = 6v 26 a feedback reference voltage close loop, vdd = 3.3v 1.25 v switching frequency vdd = 3.3v 1200 khz maximum duty vdd = 3.3v 95 % sw on resistance vdd = 3.3v 200 m ? current limit setting vdd = 3.3v 1.5 a line regulation v in = 1.5 ~ 2.5v, il = 1ma 55 mv/v load regulation v in = 2.5v, il = 1 ~ 100ma 0.2 mv/ma temperature stability for v out 50 ppm/ thermal shutdown 165 thermal shutdown hysterises 10 maximum vrs vrs 145 mv
preliminary datasheet LP6205S LP6205SC00 ver. 1.0 datasheet jul.-2013 www.lowpowersemi.com page 4 of 5 application information referring to typical application circuits, the output voltage of the switching regulator(vout) can be set with equation(1): vout=(1+r1/r2) x 1.25 v feedback loop design referring to the typical application circuits, the selection of r1 and r2 based on the trade-off between quiescent current consumption and interference immunity is stated below: for applications without standby or suspend modes, lower values of r1 and r2 are preferred. for applications concerning the current consumption in standby or suspend modes, the higher values of r1 and r2 are needed. such high impedance, which requires careful pcb layout and avoid any interference. especially to fb pin. to improve the system stability a proper value capacitor between fb pin and gnd pin is suggested. an empirical suggestion is around 220pf. pcb layout guide pcb layout shall follow these guidelines for better system stability: 1. a full gnd plane without any gap break. 2. vdd to gnd bypass cap-the 1uf mlcc noise bypass cap pin4 shall have short and wide connections. 3. vin to gnd bypass cap-add a cap close to the inductor when vin is not an idea voltage source. 4. minimize the fb node copper area and keep it far away from noise sources. 5. i follow equation(1) 6. i higher r reduces the quiescent current(path current=1.25v/r2),however resistors beyond 5m/w are not recommended.
preliminary datasheet LP6205S LP6205SC00 ver. 1.0 datasheet jul.-2013 www.lowpowersemi.com page 5 of 5 packaging information sot23-6
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